High resolution digital-to-analog (DAC) circuits are commonly used in many communication circuits. For example, broadband and high-speed (e.g., 10 Gigabit) Ethernet communication circuits may use multi-GHz and high-resolution DAC circuits. Large-amplitude push-pull DAC circuits may include switches (e.g., PMOS switches) that can be driven from a high-voltage domain (e.g., 3.3V) supply voltage. The DAC circuits, however, have to be able to operate with low-voltage domain (e.g., 0.8V-1.2V) input digital signals that are data-dependent. Therefore, the input digital signal has to pass through a level-shift circuit that can convert the voltage level of the input digital signal from the low-voltage domain to the high-voltage domain, for the DAC circuit to function properly.
Existing level-shift circuits may suffer from a number of drawbacks, for example, level translators typically do not shift the “0” level of the signal (e.g., associated with a low-voltage supply), use a large chip area, or are power hungry. Shifting the “0” level of the signal is desired when the signal is being used as an input to a large-amplitude push-pull DAC circuit with thin-oxide PMOS switch. Additionally, some traditional level-shift circuits do not operate properly with data-dependent digital signals (e.g., return-to-zero signals) and are suitable for fixed duty cycle input signals (e.g., clock signals). The high-power consumption of the existing solutions may arise from driving the current through the DAC switch from a high voltage supply, or using power hungry on-chip low-dropout (LDO) regulators.